Prof. Henry Chung (Chair, TC6 of IEEE Power Electronics Society) gave a welcoming remarks. He introduced PELS and brief the program. He added the society would arrange more technical events on Power Electronics in near future.
The first speaker was Ms. Rozalia Beica (CTO, Advanced 3D Packaging and Semiconductor Manufacturing Business Unit Manager, Yole Development) and her topic entitled "Advanced 3D Packaging Market Trends and Applications". Ms. Beica presentation included advanced packaging overview, 2.5 & 3D packaging, market forecasts and IP activities.
Ms. Becia said about 16% of overall semiconductor IC wafers were manufactured with packaging features (e.g. bumping, RDL, TSV, etc...) processed at the wafer-scale in 2012.
There were three types of 3D IC Market Drivers included Performance driven (e.g. CPU, DRAM), Form Factor-driven (e.g. Sensors, RF-SIP) and Cost-driven (e.g. FPGA). Moreover, 3D TSV applications were mentioned such as Imaging, MEMS & Sensors, RF, Power, Analog & Mixed Signal, and Logic 3D-SiP/SoC. The following diagram showed different Markets for 3D ICs.
Then Ms. Becia briefed different characteristics of Patents Filing for 3D IC Technology. Patents in domain mainly filed by firms or universities that located in USA was 56% and Korea was 18%. These patents were mainly extended in USA, China, Korea, Taiwan and Japan. Top 10 inventors for 3D IC Patents were belong to TSMC, StatsChipPAC, Micron and Samsung. Finally, she concluded that a significant growth for 2.5 / 3D IC and other TSV based applications were observed.
The second speaker was Mr. Farhang Yazdani (President and CTO, BroadPak Corporation) and his presentation named "Advances in 2.5D/3D Silicon Interposer Packaging Technology". Mr. Yazdani introduced 2.5D / 3D packaging structures and TSV synthesis.
The 2.5D and 3D Silicon Interposer were explained. After that he introduced silicon interposer formation process and signaling. The following diagram described different End-to-End Pathfinding for 3D IC included Thin and Rigid Interposer Flow.
Finally, he summarized the challenges on 2.5D / 3D as follows:
I) Thin Interposer included Supply Chain Infrastructure, Thermal-Stress Management, Reliability, IO Standardization, Pathfinding Methodology, Test Methodology and Cost;
II) Rigid Interposer included IO Standardization, Pathfinding Methodology and Test Methodology.
Mr. Chang-Sheng Chen (Manager, Advances Packaging Technology Division of Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, Taiwan (ITRI)) was the third speaker and his presentation title was "An Introduction of Development Project Power Module Packaging in ITRI". Mr. Chen shared different projects on Power Module packaging. Then he introduced their self-developed equipment for Power Module Packaging.
Mr. Chen briefed three projects which demonstrated the trend going to high power and integration. He concluded that high temperature stable conductive joint was one of the focuses in the application of power modules. Dielectrics with higher thermal conductivity were also be the key materials. At the end, he introduced Wide Band Gap Power Electronics Consortium (WPEC) for more information. (http://wpec.org.tw/eng/)
Dr. Daniel Shi (R&D Director, ASTRI) was the forth speaker and his topic was "3D High Power IGBT Module". Dr. Shi introduced ASTRI's Through-Silicon-Via (TSV) Roadmap firstly. And then he summarized their 3D Packaging Design Capability.
ASTRI's TSV process capability was also discussed and it included "Wafer Thinning & Thin Wafer Handling", "Via Formation & Isolation", "Barrier & Seed Layer", "Via Filling & Bumping" and "3D Integration for 3D Systems". The following diagram demonstrated TSV for different products.
Finally, Dr. Shi briefed Insulated Gate Bipolar Transistor (IGBT) feature and applications included Electric Vehicle. The following diagram showed the evolution of IGBT technologies. He concluded High-end IGBT module development faced many technical challenges especially on interconnect long-term reliability, module harsh environment failure and super high heat dissipation.
Dr. HL Yiu (Head of Electronics Cluster, BDTS, HKSTPC) was the last speaker in the morning session and his topic named "Infrastructure and Support at Hong Kong Science Park for the Development of 3D IC Technology".
Dr. Yiu introduced HKSTPC new laboratories named "3D SiP Lab" and "3D WLP Lab"; as well as achieved the status of National IC Design Base.
In addition, the existing laboratories and new laboratories were completed the whole IC testing service as following diagram. Dr. Yiu mentioned four 3D IC challenges included Design, Testing, Reliability and Analysis.
Because I was in-charge for another seminar and missing the afternoon session.
Prof. Ricky S.W. Lee (Professor of Mechanical Engineering and Director of Centre for Advanced Microsystems Packaging, HKUST) was the speaker in afternoon session and his presentation entitled "Emerging Trends of Packaging Structure and Interconnection for Microelectronics"
Panel Discussion chaired by Prof. Henry Chung.
Reference:
HKSTPC - http://www.hkstp.org/HKSTPC/en_html/en_index.jsp
ASTRI - http://www.astri.org/main/
沒有留言:
發佈留言